⬡ VGA TIMING STUDIO
FPGA Engineering Lab v2.4.1
VGA
● LIVE
25.175 MHz
640 × 480
Timing Presets
Resolution & Timing
H ACTIVE
V ACTIVE
Horizontal Blanking
H FRONT
H SYNC
H BACK
Vertical Blanking
V FRONT
V SYNC
V BACK
Sync Polarity
HSYNC
NEG (−)
POS (+)
VSYNC
NEG (−)
POS (+)
Refresh Rate
60
Hz
24 Hz
240 Hz
30
60
75
120
FPGA Target
VENDOR / FAMILY
Xilinx — Artix-7
Xilinx — Kintex UltraScale
Xilinx — Zynq-7000
Intel — Cyclone V
Intel — Arria 10
Lattice — iCE40
Lattice — ECP5
Gowin — GW1N
450
MAX CLK (MHz)
✓ OK
CLK FEASIBILITY
MMCM
PLL TYPE
Vivado
TOOLCHAIN
Color Depth
BITS PER CHANNEL
4-bit
8-bit
10-bit
12-bit
CRT / RASTER SCAN PREVIEW
Pixel Clock & Key Metrics
25.175
MHz
Pixel Clock
60.00
fps
Frame Rate
31.47
kHz
Line Freq
0.605
Gbps
Bandwidth
Pixel Clock Utilization
Timing Parameters
Engineering Utilities
800
H TOTAL px
525
V TOTAL lines
75.6%
ACTIVE DUTY
0.88 MB
FRAME BUFFER
31.78μs
LINE TIME
16.67ms
FRAME TIME
HDL Code Generator
↓ .v
⎘ Copy
Verilog
SystemVerilog
VHDL
TCL Constraints
Export & Tools
⬡ JSON Config
↓ Testbench
↓ .xdc
▸ Validation Console
Clear